High-Speed Test Access for Chiplets, CPC, and CPO: Die, Substrate, and Package-Level Solutions
Attendees of this webinar will learn how high-density, solderless electrical access supports characterization of processors, switches, and custom ASICs at die, substrate, and package levels. Increasing data rates leave less […]
Characterizing Front Panel I/O: Reliable Host and Module Testing for 1.6T and 3.2T Systems
As datacenter systems scale toward 1.6T and 3.2T architectures, front panel I/O is becoming a more critical point for electrical characterization. Higher lane rates increase sensitivity to breakout geometry, transition […]