High-Speed Test Access for Chiplets, CPC, and CPO: Die, Substrate, and Package-Level Solutions
Attendees of this webinar will learn how high-density, solderless electrical access supports characterization of processors, switches, and custom ASICs at die, substrate, and package levels. Increasing data rates leave less insertion loss budget for test fixtures, while chiplet PHY validation and the development of co-packaged copper (CPC) and co-packaged optics (CPO) introduce new test access […]